DFI - Ddr-phy.org

AUSTIN, Texas, Might 2, 2018 - The DDR PHY Interface (DFI) Group at present launched version 5.0 of the specification for interfaces between excessive-speed memory controllers and physical (PHY) interfaces to help the requirements of future mobile and server memory requirements. The DFI specs, extensively adopted all through the memory trade, allow better interoperability. The DFI Group included a number of interface improvements on this latest specification. The new model of the specification adds protocol support for the most recent DDR and MemoryWave Community low-power memory applied sciences. Earlier versions of the specification defined memory coaching throughout the interface between the memory controller and the PHY. The brand new specification utterly transitions to PHY-unbiased coaching mode where the PHY trains the memory interface with out involving the controller. Other interface enhancements include lower energy enhancements, offering a PHY-independent boot sequence, expanding frequency change assist, and defining new controller-to-PHY interface interactions. "The industry is starting to embrace new low-power and DDR memory technologies, including excessive-performance devices akin to servers, storage, and networking; autonomous automobiles; and low-energy handheld devices and IoT," stated John MacLaren, DFI Group chairman and Cadence design engineering architect.

"The DFI Group, consisting of experts from main companies in the industry, is enthusiastic to contribute to enabling this transition with the newest launch of the DFI specification. "Adopting open and standard interfaces like the brand new DFI 5.0 specification for top-speed memory controller and PHY interface allows AMD to efficiently and effectively undertake new memory requirements as we ship high-performance products to our customers. "Cadence has been a key contributor to the DFI 5.Zero standard, which helps to ensure interoperability between DDR PHYs and DDR controllers, particularly for future memory devices," mentioned Marc Greenberg, Memory Wave group director, product marketing, DDR, HBM, flash/storage and MIPI IP. "As a number one supplier of DDR IP and Verification IP, Synopsys makes significant investments to make sure that our DesignWare® controller and PHY IP are compliant to business standards akin to DFI," stated Navraj Nandra, Sr. Director of promoting for Interface and Analog IP solutions at Synopsys.

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